(a) Field of the Invention
The invention relates to a control system for a dynamic RAM (hereafter referred to as DRAM), and more particularly, to a control system for a DRAM in a computer system in which a system memory is shared by two control sections such as a memory controller and an external device, for example.
(b) Description of the Related Art
To increase the throughput for a read/write operation in DRAMs, a burst transfer mode is increasingly adopted, and proposals are made for DRAM having a plurality of banks. Examples of the proposed DRAM which have a plurality of banks and which are proposed as DRAMs of the next generation include a synchronous DRAM (hereafter referred to as SDRAM) and Rambus DRAM. These involve a pipeline control of the plurality of banks.
In an image display system which involves an image processing, for example, there is proposed a UMA technique (Unified Memory Architecture) in which a system memory such as DRAM is shared by a memory controller and an external device such as an image display unit. A method of controlling a DRAM in a system which employs a conventional UMA technique will be described below with reference to a block diagram shown in FIG. 5.
A system memory 11 which is implemented by DRAMs is controlled by a memory controller 12 and an external device 13, each of which is controlled by CPU 10. The memory controller 12 and the external device 13 each controls the system memory 11 by feeding an address thereto through an address bus 14 and also feeding a control signal comprising XRAS (row address strobe; here XRAS stands for a top bar attached to RAS, and the character X is similarly applied in other occurrences), XCAS (column address strobe), XWE (write enable) and XOE (output enable) or the like through control signal lines 16, and transmits data to or receives data from the system memory 11 through a data bus 15. Both the memory controller 12 and the external device 13 transmit/receive a memory request signal XMREQ and a memory use grant signal XMGNT to determine which one of them has the privilege to use the system memory 11.
FIG. 6 is a series of timing charts illustrating, as an example, signals appearing in a system which uses SDRAM and which employs the UMA technique. Upon reception of a memory request signal XMREQ from the external device, the memory controller which then has the privilege to use the memory either grants the use of the memory immediately whenever the memory controller is not using the system memory, or, if the system controller itself is using the system memory as illustrated in FIG. 6, establishes a floating (high impedance) state on the control signal lines and the address bus and activates the memory use grant signal XMGNT upon termination of its own access followed by the precharge operation. Thereupon the privilege to use the system memory is transferred to the external device, which is then enabled to access the system memory. FIG. 6 illustrates an example in which the memory controller reads data xm1-xm4 from the bank A of the system memory, followed by the external device reading data yn1-yn4 from the bank B of the system memory.
In the DRAM control system which operates according to the conventional UMA technique, whenever the privilege to use the system memory is changed, a pipeline operation which is then in progress is interrupted to exchange the privilege. When the privilege is exchanged, it is also necessary to provide a processing such as a precharge operation of the system memory, thus consuming a lot of time for the exchange. By way of example, FIG. 6 shows a situation in which after data xm1-xm4 is read out at time T10, the system must wait for until time T17 before next data yn1-yn4 can be read out. In this manner, a memory control system which has the current UMA technique requires a lot of time in exchanging the privilege to use the system memory, thus hindering to achieve a higher rate operation of a computer system. Accordingly, it is desired to provide a control system for DRAM in a system constructed by a UMA technique which is capable of reducing the time expended for the exchange, thereby enabling the achievement of a higher rate operation of the computer system.